This application is a continuation-in-part of USSN 240,159, MOS Integrated Circuit With Vertical Shield, filed Aug. 26, 1988 and, assigned to the assignee of this invention, abandoned.
This invention relates to MOS integrated circuits, and particularly to such circuits covered by a dielectric passivation layer which can provide a capacitive parasitic communication path between signal carrying elements in separate signal processing circuits within the integrated circuit.
It sometimes occurs that, due to the constraints of circuit arrangements and space, signal carrying elements of two separate and desirably isolated circuits must be placed adjacent each other and in contact with the passivation layer of the integrated circuit. In this situation, the dielectric passivation layer can provide a horizontal parasitic capacitive coupling between the signal carrying elements that allows crosstalk between the circuits of high frequency elements in one of the signals. If one of the signal carrying elements cannot be moved to a different location on the chip, it would be desirable to provide a grounded shield between the elements to prevent such horizontal coupling. Shielding devices in the prior art, however, have either been of little effectiveness in providing shielding in a horizontal direction or have required extra steps and therefore extra expense in the fabrication process.